1. Field of the Invention
The present invention generally relates to an analog-to-digital conversion unit (ADC unit), and more particularly, to an ADC unit and an analog-to-digital converting method (ADC method) thereof able to increase the conversion accuracy.
2. Description of Related Art
In the modern time, the computer has become indispensable means for the modern people. Since a digital data is easier for editing, analyzing, storing and more robust against noise, the most of information currently are in digital format so as to facilitate storing and processing. In order to convert analog information (such as temperature, humidity, luminance, sound) into a digital data, an analog-to-digital converter is used for converting the format of the analog information. Besides, along with the progress of since and technology, the sampling precision of an analog-to-digital converter on analog information is advanced, so that the conformability between the digital data obtained through high-precision converting and the corresponding environment information is higher, wherein the adopted high-precision analog-to-digital converter is, for example, a pipelined analog-to-digital converter.
FIG. 1 is a block diagram of a pipelined stage in a conventional pipelined analog-to-digital converter and FIG. 2 is a conversion characteristic curve graph of a pipelined analog-to-digital converter. Referring to FIGS. 1 and 2, in a pipelined stage 100 of a pipelined analog-to-digital converter, the pipelined stage 100 includes an ADC unit 110. The ADC unit 110 is coupled to a digital-to-analog converter 120 and produces a digital data DOUT according to an input voltage VIN. The digital-to-analog converter 120 converts the digital data DOUT into an analog output voltage VOUT.
A sub analog-to-digital converter 111 herein compares the input voltage VIN respectively with two threshold voltages VTH1 and VTH2 and then outputs two bits B1 and B2 according to the comparison result. Another sub analog-to-digital converter 112 herein compares the input voltage VIN respectively with another two threshold voltages VTH3 and VTH4 and then outputs two bits B3 and B4 according to the comparison result. Further, yet another sub analog-to-digital converter 113 herein compares the input voltage VIN respectively with yet another two threshold voltages VTH5 and VTH6 and then outputs two bits B5 and B6 according to the comparison result. An encoding unit 314 encodes the bits B1, B2, B3, B4, B5 and B6 and then outputs the digital data DOUT.
The sub analog-to-digital converter usually employs a comparator for comparing voltages, wherein the offset error of the comparator would affect the voltage level of the threshold voltage. Taking the sub analog-to-digital converter 111 as an example, the offset error of the comparator may make the voltage level of the threshold voltage VTH1 shift towards the threshold voltage VTH2. In the above-mentioned circumstance, if the sub analog-to-digital converter 111 compares the input voltage with a shifted threshold voltage, the output bits B1 and B2 may be incorrect ones, and moreover, the ADC unit 110 would output incorrect digital data.